Texas Instruments
Sitara AM62Dx EVM Demo
BREAKDOWN
The TI Sitara AM62Dx EVM Multicore Audio Weaver SDK provides a cohesive platform for audio signal chain processing development on TI’s new C7x DSP, powered by a robust and seamless C7x DSP and ARM Cortex-A53 “plug-and-play” multicore integration with DSP Concepts’ embedded and optimized Audio Weaver Core libraries.
KEY FEATURES
- Highly optimized audio kernels for TI C7x ISA
- Kernel support for latency critical automotive audio use-cases
- Multi-Instance audio processing enablement via Audio Weaver
- Primary processing core: TI C7x DSP
- ADC/DAC I/O and configuration
- Secondary processing core: ARM Cortex-A53
- Simplified inter-processor communication enablement
- Distribute audio processing across heterogeneous AM62Dx processors within a single unified audio processing signal flow via shared memory
- Primary processing core: TI C7x DSP
- Multi-rate and multi-threaded audio processing enablement
- Mix and match audio data processing transfer rates within a single unified audio processing signal flow
- Low-latency audio path for latency critical audio requirements and solutionsMulti-rate and multi-threaded audio processing enablement
- Realtime Embedded Tuning Interface
- MCU/R5F is tuning gateway
- Multiple real-time tuning interfaces available via data protocols
- UART
- TCP/IP
- Ethernet Audio Video Bridge (AVB) Support
- Audio over ethernet per IEEE 1722 protocol
- Single multichannel PCM audio stream
- Duplex telephony support
- 8ch Tx / 8ch Rx
- Duplex telephony support
Use Cases
- In-car communication (ICC)
- Navigation and safety prompts/chimes
- Road Noise Cancellation (RNC) / Engine Order Cancellation (EOC)
- Acoustic Cabin Correction (Entertainment Tunings and Presents)
- Telephony (Voice Communication)
- Exterior Sound Enhancement (e.g. Pedestrian warning speaker, exterior voice interaction, etc…)
- Engine Sound Synthesis (ESS) \ Engine Sound Enhancement (ESE)
- Acoustic Vehicle Alert System (AVAS)
- Object-Based Audio (OBA)
HARDWARE AND PROCESSING SPECS
- TI C7x DSP
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- Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
- Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with ParityQuad ARM Cortex-A53 (1.4GHz)
- ARM Cortex-M4F (400MHz)
- 256KB SRAM with SECDED ECC
- ARM Cortex-R5F
- Armv7-R architecture
- R5FSS Memory System
- 32KB Instruction Cache
- 4x8KB ways
- SECDED ECC protected per 64 bits
- 32KB Data Cache
- 4x8KB ways
- SECDED ECC protected per 32 bits
- 64KB tightly-coupled memory (TCM) per CPU
- SECDED ECC protected per 32 bits
- TCM hard error cache Implemented in CPU
- Readable/writable from system
- TCMs initialized (to 0's) at reset
- 32KB TCMA (ATCM)
- 16KB TCMB0 (B0TCM)
- 16KB TCMB1 (B1TCM)
- 32KB Instruction Cache
- Full-precision Floating Point (VFPv3)
16-region Memory Protection Unit (MPU) - 8 breakpoints, 8 watch points
- CoreSight Debug Access Port (DAP)
- CoreSight ETM-R5 interface (CTI, ETM)
- Performance Monitoring Unit (PMU)
- 32-bit to 36-bit Region-based Address Translation (RAT) on memory access initiators
- Integrated Vectored Interrupt Manager (VIM) per core with 256 Interrupt Inputs each
- Programmable interrupt priority (4-bit)
- Programmable interrupt enable mask
- Software-generated interrupts
- Synchronous clock domain crossing on all core interfaces
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